The design and test of modern electronic devices, such as embedded processors (EP) and systems-on-a-chip (SoC) is a complex process involving many stages. For example, many systems, such as mobile devices, networking products, and modems require new embedded processors (EP). These EPs can either be general purpose, such as microcontrollers and digital signal processors (DSP), or application specific, using application specific instruction set processors (ASIP). Compared to general-purpose processors, ASIPs provide a tradeoff of computational performance and flexibility on the one hand and power consumption on the other. Therefore, ASIPs that are designed to execute specific tasks very efficiently can be found in a wide range of embedded systems.
However, designing systems with ASIPs is far more complex than assembling systems with standard processors. Typically, designing ASIPs comprises an iterative exploration in which hardware and software are explored and modified. This iterative process is referred to as an architecture exploration loop. The architecture exploration typically requires a number of tools, such as an assembler, linker, and simulator. If hardware and software are available, profiling results are acquired that usually lead to architecture modifications making the processor more efficient. To be consistent with these modifications, the software tools potentially need to be changed, as well.
Moreover, the overall design time can be significantly reduced by introducing into the architecture exploration loop a retargetable compiler that reflects the target architecture. Besides reducing the implementation and verification time, the availability of a compiler also increases the system reusability for similar applications.
In contrast to traditional compilers that target only a single processor architecture, retargetable compilers can be altered to generate code for different target processor architectures due to an editable target architecture model. Thus, the retargetable compiler can be used in the architecture exploration phase. Further, retargetable compilers (possibly enhanced with target-specific code optimization techniques) can be used to quickly generate production compilers for the ASIP IP end users for application software development. Thus, efficient architecture exploration and design of ASIPs requires retargetable software development tools, in particular compilers that can be quickly adapted to new target architectures.
One design approach is to model the target architecture in a dedicated description language (ADL) and to generate some tools automatically from the ADL specification. For compiler generation, however, most existing systems are limited either by the manual retargeting effort or by redundancies in the ADL models that lead to potential inconsistencies.
In the context of ASIP design, where a tight link to hardware and system on a chip (SoC) design flows is required, two mainstream approaches to retargetable compilation can be identified. The first one builds on a predefined, yet configurable processor core that can be optimized by the user via addition of custom machine instructions. In this case, semi-custom compiler systems can be used, and retargeting is implemented by making new instructions available to the compiler in the form of “intrinsics.” While this approach offers the advantage of reusing well-proven compiler tools, it restricts the flexibility of the ASIP designer and requires manual (and non-portable) software source code modifications.
The second approach is based on the paradigm of architecture description languages (ADLs) that permit high-level (e.g., beyond Register Transfer Level or RTL) modeling of processors for early design phases such as architecture exploration and system-level verification. A challenge in retargetable compilation based on ADL models, however, is the large variety of potential target architectures, which is essentially only limited by the ADL's capabilities. The ADL approach permits very high flexibility in ASIP design, but demands advanced techniques for efficient compiler retargeting.
A detailed overview of work related to compiler generation from processor architecture description languages (ADLs) or compiler specifications is given by R. Leupers and P. Marwedel in, “Retargetable Compiler Technology for Embedded Systems,” Kluwer Academic Publishers, Boston, October 2001, which is incorporated herein as background material.